1. Field of the Invention
The present invention relates to a data output buffer for externally transmitting data read in memory cells of a semiconductor memory device via output lines, and more particularly to such a data output buffer capable of minimizing generation of ground noise in data of low logic.
2. Description of the Prior Art
Data output buffers employed in typical semiconductor memory devices such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) have a function for matching input impedance of an external circuit device connected to an output line with output impedance of a sense amplifier for sensing and amplifying data from a memory cell. Such data output buffers need a transistor with a high channel width and supply voltages exhibiting a high voltage level difference because of a relatively high input impedance of the external circuit device. The high channel-width transistor varies steeply the current on the output line at both the leading and trailing edges of output data, thereby generating noise at the edge portions of output data. The noise generated in the output data becomes larger as the voltage level difference between the supply voltages goes up.
Among noise involved in output data, those included in high logic involve a steep variation and have a large amount of current, as compared to those included in low logic. For this reason, the conventional data output buffers may have an adverse effect of damaging external circuit devices connected to output lines and output drivers. Such a problem encountered in the conventional data output buffers will be described in detail, in conjunction with FIG. 1.
FIG. 1 is a circuit diagram of one example of the conventional data output buffers. As shown in FIG. 1, the data output buffer includes a first NOR Gate 10 for receiving true data/TD of low logic from a first input line 11 and a second NOR Gate 12 for receiving complement data/CD of low logic from a second input line 13. The first NOR gate 10 selves to invert the true data/TD received from the first input line 11 in response to a low logic signal received from a first inverter 14 and then transmit the inverted true data/TD to a second inverter 16. In similar, the second NOR Gate 12 serves to invert the complement data /CD received from the second input line 13 in response to a low logic signal received from a first inverter 14 and then transmit the inverted complement data/CD to the gate of an NMOS transistor 20 via a node 17. The first inverter 14 inverts an enable signal EN applied to a control line 15 and then sends the inverted enable signal to both the first NOR Gate 10 and the second NOR Gate 12. Consequently, the first and second NOR Gates 10 and 12 perform their transmission operations when an enable signal EN of high logic is applied to the control line 15.
On the other hand, the second inverter 16 inverts the already inverted true data from the first NOR gate 10 again and then sends the resultant true data to the Gate of a PMOS transistor 18 via a node 19. The PMOS transistor 18 is turned on when true data of low logic from the second inverter 16 is applied to the gate thereof. The activated PMOS transistor 18 supplies a supply voltage from a first power supply source Vcc to an output line 21, so that data of high logic can be outputted through the output line 21. The NOMS transistor 20 is turned on when the inverted complement data from the second NOR Gate 12 applied to the Gate thereof has high logic. The activated NMOS transistor 20 supplies a supply voltage from a second power supply source, namely, Ground GND to the output line 21, so that data of low logic can be transmitted to the external circuit device via the output line 21.
In this conventional data output buffer, however, current flowing from the output line 21 to the ground GND via the NMOS transistor 20 is steeply decreased in amount because of a steep increase in current at the leading edge of the output signal from the second NOR gate 12 being applied to the node 17. As a result, the ground noise is generated at the trailing edge of data transmitted to the external circuit device via the output line. Furthermore, the conventional data output buffer generates, in output data, a noise signal with a higher current variation depending on the peak output current and time as the voltage level difference between the power supply sources Vcc and GND goes up.